An integrated circuit (IC) includes a serial-to-parallel converter configured to receive a serial input signal to provide one or more parallel output signals. The serial input signal is an M-level Pulse-Amplitude Modulated (PAM) signal, wherein M is a positive integer. The serial-to-parallel converter includes a data converter configured to receive the serial input signal and provide a data converter output signal. The data converter output signal represents information of the serial input signal with N1 bits, and N1 is a positive integer. An encoder is configured to encode the data converter output signal to provide encoder output signal with N2 bits, wherein N2 is a positive integer less than half of N1. One or more sub-deserializers are configured to receive the encoder output signal and generate the one or more parallel output signals.