发明授权
- 专利标题: Step-down circuit
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申请号: US15250816申请日: 2016-08-29
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公开(公告)号: US09735682B1公开(公告)日: 2017-08-15
- 发明人: Motoki Tamura
- 申请人: KABUSHIKI KAISHA TOSHIBA
- 申请人地址: JP Tokyo
- 专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人: Kabushiki Kaisha Toshiba
- 当前专利权人地址: JP Tokyo
- 代理机构: Patterson & Sheridan, LLP
- 优先权: JP2016-051270 20160315
- 主分类号: H02M3/07
- IPC分类号: H02M3/07 ; H02M3/158
摘要:
A step-down circuit includes a first transistor of N-type having a channel between an input terminal and a first node, and a gate to which a reference voltage that is lower than a peak value of an AC voltage applied to the input terminal is applied, a second transistor of P-type having a channel between the input terminal and a second node, and a gate to which the reference voltage is applied, a third transistor of N-type having a channel between the first node and an output terminal, and a gate to which the AC voltage is applied, a fourth transistor of P-type having a channel between the second node and the output terminal, and a gate to which the AC voltage is applied, a first capacitor connected between the first node and the second node, and a second capacitor connected between the output terminal and a reference potential terminal.
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