Invention Grant
- Patent Title: Reducing memory overhead associated with memory protected by a fault protection scheme
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Application No.: US14573259Application Date: 2014-12-17
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Publication No.: US09747035B2Publication Date: 2017-08-29
- Inventor: Rakesh Kumar , Xun Jian
- Applicant: Empire Technology Development LLC
- Applicant Address: US DE Wilmington
- Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Current Assignee: EMPIRE TECHNOLOGY DEVELOPMENT LLC
- Current Assignee Address: US DE Wilmington
- Agency: Turk IP Law, LLC
- Main IPC: G11C29/00
- IPC: G11C29/00 ; G06F3/06 ; G06F11/10 ; G06F11/14 ; G11C7/10 ; G06F11/16

Abstract:
A memory request initiates access to a memory location in the memory. The memory location is evaluated to determine whether the memory location is located within a first portion of the memory or within a second portion of the memory. In response to determining that the memory location is located within the first portion and that the memory request is a read request, the memory location located within the first portion is accessed. In response to determining that the memory request is a write request and the memory location is located within the first portion, the memory location located within the first portion and a duplicate of the memory location is accessed. When the memory location is located within the second portion, the memory location located within the second portion using a redundant array of independent disks (RAID) memory mechanism, in response to the memory request being the write request.
Public/Granted literature
- US20160179370A1 Reducing Memory Overhead Associated With Memory Protected By A Fault Protection Scheme Public/Granted day:2016-06-23
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