- 专利标题: Through-body via liner deposition
-
申请号: US15124820申请日: 2014-07-08
-
公开(公告)号: US09748180B2公开(公告)日: 2017-08-29
- 发明人: Puneesh Puri , Jiho Kang , James Y. Jeong
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Finch & Maloney PLLC
- 国际申请: PCT/US2014/045781 WO 20140708
- 国际公布: WO2016/007141 WO 20160114
- 主分类号: H01L29/00
- IPC分类号: H01L29/00 ; H01L23/00 ; H01L21/762 ; H01L29/06 ; H01L23/48 ; H01L21/768 ; H01L23/532
摘要:
Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together.
公开/授权文献
- US20170018509A1 THROUGH-BODY VIA LINER DEPOSITION 公开/授权日:2017-01-19
信息查询
IPC分类: