Invention Grant
- Patent Title: Through-body via liner deposition
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Application No.: US15124820Application Date: 2014-07-08
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Publication No.: US09748180B2Publication Date: 2017-08-29
- Inventor: Puneesh Puri , Jiho Kang , James Y. Jeong
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- International Application: PCT/US2014/045781 WO 20140708
- International Announcement: WO2016/007141 WO 20160114
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L23/00 ; H01L21/762 ; H01L29/06 ; H01L23/48 ; H01L21/768 ; H01L23/532

Abstract:
Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together.
Public/Granted literature
- US20170018509A1 THROUGH-BODY VIA LINER DEPOSITION Public/Granted day:2017-01-19
Information query
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