- 专利标题： Tap dual port router circuitry with gated shiftDR and clockDR
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申请号： US15340507申请日： 2016-11-01
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公开(公告)号： US09753085B2公开(公告)日： 2017-09-05
- 发明人: Lee D. Whetsel
- 申请人： TEXAS INSTRUMENTS INCORPORATED
- 申请人地址： US TX Dallas
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： US TX Dallas
- 代理商 Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- 主分类号： G01R31/3177
- IPC分类号： G01R31/3177 ; G01R31/3185 ; G01R31/317
摘要：
This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
公开/授权文献
- US20170045581A1 3D STACKED DIE TEST ARCHITECTURE 公开/授权日：2017-02-16
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