Invention Grant
- Patent Title: 3D integration using Al—Ge eutectic bond interconnect
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Application No.: US15040823Application Date: 2016-02-10
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Publication No.: US09754922B2Publication Date: 2017-09-05
- Inventor: Peter Smeys , Mozafar Maghsoudnia
- Applicant: InvenSense, Inc.
- Applicant Address: US CA San Jose
- Assignee: InvenSense, Inc.
- Current Assignee: InvenSense, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L25/065 ; H01L25/00 ; H01L23/00
Abstract:
Provided herein is an apparatus including a first CMOS wafer and a second CMOS wafer. A number of eutectic bonds connect the first CMOS wafer to the second CMOS wafer. The eutectic bond includes combinations where the eutectic bonding temperature is lower than the maximum temperature a CMOS circuit can withstand without being damaged during processing.
Public/Granted literature
- US20160233197A1 3D INTEGRATION USING Al-Ge EUTECTIC BOND INTERCONNECT Public/Granted day:2016-08-11
Information query
IPC分类:
