Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor substrate. At least one through-semiconductor via is formed in the semiconductor substrate and an interlayer dielectric layer is formed overlying the at least one through-semiconductor via and the plurality of semiconductor devices. A first pattern is etched in the interlayer dielectric layer over the at least one through-semiconductor via, and a second pattern different from the first pattern is etched in the interlayer dielectric layer over the same through-semiconductor via as the first pattern. At least one interconnect via is embedded within the interlayer dielectric layer, in electrical communication with one of the at least one through-semiconductor vias. A metal-containing material is deposited in the first pattern and the second pattern to form a first metal layer in electrical communication with the at least one interconnect via.