Invention Grant
- Patent Title: Chroma cache architecture in block processing pipelines
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Application No.: US14472119Application Date: 2014-08-28
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Publication No.: US09762919B2Publication Date: 2017-09-12
- Inventor: Guy Cote , Joseph P. Bratt , Timothy J. Millet , Shing I. Kong , Joseph J. Cheng
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Agent Robert C. Kowert
- Main IPC: H04N19/127
- IPC: H04N19/127 ; H04N19/176 ; H04N19/186 ; H04N19/423 ; H04N19/433 ; G06F12/00 ; H04N19/42 ; H04N19/172 ; G06T1/60

Abstract:
Methods and apparatus for caching reference data in a block processing pipeline. A cache may be implemented to which reference data corresponding to motion vectors for blocks being processed in the pipeline may be prefetched from memory. Prefetches for the motion vectors may be initiated one or more stages prior to a processing stage. Cache tags for the cache may be defined by the motion vectors. When a motion vector is received, the tags can be checked to determine if there are cache block(s) corresponding to the vector (cache hits) in the cache. Upon a cache miss, a cache block in the cache is selected according to a replacement policy, the respective tag is updated, and a prefetch (e.g., via DMA) for the respective reference data is issued.
Public/Granted literature
- US20160065973A1 CHROMA CACHE ARCHITECTURE IN BLOCK PROCESSING PIPELINES Public/Granted day:2016-03-03
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