A circuit having a first, second, and third capacitor. Capacitor plates of the capacitors are connected to a first circuit node. The circuit supplies a first time-dependent voltage to the first capacitor, a second time-dependent voltage to the second capacitor, and a third time-dependent voltage to the third capacitor. The first and second voltages are clocked in antiphase. The second and third voltages are clocked in phase. The circuit has an amplifier, a synchronous demodulator, and a comparator. Inputs of the amplifier are connected to the first circuit node and ground. The synchronous demodulator alternately applies an output signal of the amplifier to inputs of the comparator, synchronously with the clock frequency of the first voltage. The circuit generates a control value dependent on an output of the comparator. The circuit changes amplitudes of the first and third voltage and/or the second voltage dependent on the control value.