In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.