Invention Grant
- Patent Title: Method and structure of three-dimensional chip stacking
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Application No.: US14951813Application Date: 2015-11-25
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Publication No.: US09773768B2Publication Date: 2017-09-26
- Inventor: Chen-Hua Yu , Wen-Chih Chiou , Yung-Chi Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L25/00 ; H01L25/065 ; H01L21/56 ; H01L21/48 ; H01L23/31 ; H01L23/498

Abstract:
A method includes placing a first plurality of device dies over a first carrier, with the first plurality of device dies and the first carrier in combination forming a first composite wafer. The first composite wafer is bonded to a second wafer, and the first plurality of device dies is bonded to a second plurality of device dies in the second wafer through hybrid bonding. The method further includes de-bonding the first carrier from the first plurality of device dies, encapsulating the first plurality of device dies in an encapsulating material, and forming an interconnect structure over the first plurality of device dies and the encapsulating material.
Public/Granted literature
- US20170103973A1 Method and Structure of Three-Dimensional Chip Stacking Public/Granted day:2017-04-13
Information query
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