Invention Grant
- Patent Title: Relaxed semiconductor layers with reduced defects and methods of forming the same
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Application No.: US15002078Application Date: 2016-01-20
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Publication No.: US09773906B2Publication Date: 2017-09-26
- Inventor: Wei-E Wang , Mark S. Rodder , Ganesh Hedge , Christopher Bowen
- Applicant: Wei-E Wang , Mark S. Rodder , Ganesh Hedge , Christopher Bowen
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Suwon-si
- Agency: Myers Bigel, P.A.
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/78 ; H01L21/764 ; H01L21/02 ; H01L21/308 ; H01L29/04

Abstract:
Methods of forming a layer of silicon germanium include forming an epitaxial layer of Si1-xGex on a silicon substrate, wherein the epitaxial layer of Si1-xGex has a thickness that is less than a critical thickness, hc, at which threading dislocations form in Si1-xGex on silicon; etching the epitaxial layer of Si1-xGex to form Si1-xGex pillars that define a trench in the epitaxial layer of Si1-xGex, wherein the trench has a height and a width, wherein the trench has an aspect ratio of height to width of at least 1.5; and epitaxially growing a suspended layer of Si1-xGex from upper portions of the Si1-xGex pillars, wherein the suspended layer defines an air gap in the trench beneath the suspended layer of Si1-xGex.
Public/Granted literature
- US20160322493A1 Relaxed Semiconductor Layers With Reduced Defects and Methods of Forming the Same Public/Granted day:2016-11-03
Information query
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