Invention Grant
- Patent Title: High speed SAR ADC using comparator output triggered binary-search timing scheme and bit-dependent DAC settling
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Application No.: US15594260Application Date: 2017-05-12
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Publication No.: US09774337B1Publication Date: 2017-09-26
- Inventor: Yuan-Ju Chao , Ta-Shun Chu
- Applicant: Yuan-Ju Chao , Ta-Shun Chu
- Agency: Tran & Associates
- Main IPC: H03M1/06
- IPC: H03M1/06 ; H03M1/10 ; H03K5/24 ; H03K5/00 ; H03M1/00 ; H03M1/12
Abstract:
A method of increasing SAR ADC conversion rate and reducing power consumption by employing a new timing scheme and minimizing timing delay for each bit-test during binary-search process. The high frequency clock input requirement is eliminated and higher speed rate can be achieved in SAR ADC.
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