- Patent Title: Multiplier pipelining optimization with a bit folding correction
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Application No.: US14664669Application Date: 2015-03-20
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Publication No.: US09778910B2Publication Date: 2017-10-03
- Inventor: T. J. O'Dwyer , Pierre Laurent
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G06F7/10
- IPC: G06F7/10 ; G06F7/38 ; G06F7/533 ; G06F7/72
Abstract:
One embodiment provides a system. The system includes a register to store an operand; a multiplier; and optimizer logic to initiate a square/multiply stage to operate on the operand, initiate a reduction stage prior to completion of the square/multiply stage, and determine whether a carry propagation has occurred.
Public/Granted literature
- US20160274866A1 MULTIPLIER PIPELINING OPTIMIZATION WITH A BIT FOLDING CORRECTION Public/Granted day:2016-09-22
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