Invention Grant
- Patent Title: Interconnect structures for assembly of multi-layer semiconductor devices
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Application No.: US15327235Application Date: 2015-08-11
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Publication No.: US09780075B2Publication Date: 2017-10-03
- Inventor: Rabindra N. Das , Donna-Ruth W. Yost , Chenson Chen , Keith Warner , Steven A. Vitale , Mark A. Gouker , Craig L. Keast
- Applicant: Massachusetts Institute of Technology
- Applicant Address: US MA Cambridge
- Assignee: Massachusetts Institute of Technology
- Current Assignee: Massachusetts Institute of Technology
- Current Assignee Address: US MA Cambridge
- Agency: Daly, Crowley, Mofford & Durkee, LLP
- International Application: PCT/US2015/044608 WO 20150811
- International Announcement: WO2016/025451 WO 20160218
- Main IPC: H01L23/52
- IPC: H01L23/52 ; H01L25/065 ; H01L25/00 ; H01L23/522 ; H01L23/532

Abstract:
A multi-layer semiconductor device includes at least two semiconductor structures, each of the at least two semiconductor structures having first and second opposing surfaces and including a first section and a second section. The second section includes a device layer and an insulating layer. The multi-layer semiconductor device also includes one or more conductive structures and one or more interconnect pads. Select ones of the one or more interconnect pads are electrically coupled to the one or more conductive structures. The multi-layer semiconductor device additionally includes a via joining layer disposed between and coupled to second surfaces of each of the at least two semiconductor structures. A corresponding method for fabricating a multi-layer semiconductor device is also provided.
Public/Granted literature
- US20170200700A1 Interconnect Structures for Assembly of Multi-Layer Semiconductor Devices Public/Granted day:2017-07-13
Information query
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