Invention Grant
- Patent Title: Non-planar semiconductor device having self-aligned fin with top blocking layer
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Application No.: US14780218Application Date: 2013-06-26
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Publication No.: US09780217B2Publication Date: 2017-10-03
- Inventor: Jeng-Ya D. Yeh , Chia-Hong Jan , Walid M. Hafez , Joodong Park
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- International Application: PCT/US2013/047757 WO 20130626
- International Announcement: WO2014/209289 WO 20141231
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/423

Abstract:
Non-planar semiconductor devices having self-aligned fins with top blocking layers and methods of fabricating non-planar semiconductor devices having self-aligned fins with top blocking layers are described. For example, a semiconductor structure includes a semiconductor fin disposed above a semiconductor substrate and having a top surface. An isolation layer is disposed on either side of the semiconductor fin, and recessed below the top surface of the semiconductor fin to provide a protruding portion of the semiconductor fin. The protruding portion has sidewalls and the top surface. A gate blocking layer has a first portion disposed on at least a portion of the top surface of the semiconductor fin, and has a second portion disposed on at least a portion of the sidewalls of the semiconductor fin. The first portion of the gate blocking layer is continuous with, but thicker than, the second portion of the gate blocking layer. A gate stack is disposed on the first and second portions of the gate blocking layer.
Public/Granted literature
- US20160056293A1 NON-PLANAR SEMICONDUCTOR DEVICE HAVING SELF-ALIGNED FIN WITH TOP BLOCKING LAYER Public/Granted day:2016-02-25
Information query
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