- 专利标题: Semiconductor memory device that determines a deterioration level of memory cells and an operation method thereof
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申请号: US15232791申请日: 2016-08-09
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公开(公告)号: US09786381B2公开(公告)日: 2017-10-10
- 发明人: Yoshiki Terabayashi
- 申请人: Toshiba Memory Corporation
- 申请人地址: JP Tokyo
- 专利权人: Toshiba Memory Corporation
- 当前专利权人: Toshiba Memory Corporation
- 当前专利权人地址: JP Tokyo
- 代理机构: Patterson & Sheridan, LLP
- 优先权: JP2015-243424 20151214
- 主分类号: G11C7/00
- IPC分类号: G11C7/00 ; G11C16/34 ; G06F3/06 ; G11C16/08 ; G11C16/26 ; G11C29/12
摘要:
A semiconductor memory device includes a memory cell unit including a plurality of blocks, each of the blocks including a plurality of pages, and a circuit configured to count a number of activated or non-activated memory cells in one or more pages when a first voltage is applied to gates of memory cells of said one or more pages to read data therefrom, count a number of activated or non-activated memory cells in said one or more pages when a second voltage different from the first voltage is applied to the gates of the memory cells of said one or more pages to read data therefrom, compare the counted numbers, and store, in a register, data about deterioration of the memory cells of said one or more pages depending on a comparison result.
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