Apparatus and methods for digital step attenuators are provided herein. In certain configurations, a DSA includes a plurality of DSA stages that can be set in an attenuation mode or in a bypass mode using a plurality of switching circuits. A first switching circuit of the plurality of switching circuits includes a field effect transistor (FET) switch, a gate resistor, one or more gate resistor bypass switches, and a pulse generation circuit. The gate resistor is electrically connected between a switch control input and a gate of the FET switch, and a switch control signal can be provided to the switch control input to turn on or off the FET switch. In response to detecting a rising and/or falling edge of the switch control signal, the pulse generation circuit can control the one or more gate resistor bypass switches to bypass the gate resistor.