Invention Grant
- Patent Title: Power supply transient performance (power integrity) for a probe card assembly in an integrated circuit test environment
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Application No.: US15055089Application Date: 2016-02-26
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Publication No.: US09793226B2Publication Date: 2017-10-17
- Inventor: Thomas P. Warwick , James V. Russell , Dhananjaya Turpuseema
- Applicant: Thomas P. Warwick , James V. Russell , Dhananjaya Turpuseema
- Applicant Address: US NJ South Plainfield
- Assignee: R & D Circuits, Inc.
- Current Assignee: R & D Circuits, Inc.
- Current Assignee Address: US NJ South Plainfield
- Agency: Law Firm of Richard B. Klar
- Agent Richard B. Klar
- Main IPC: H05K1/00
- IPC: H05K1/00 ; H01L23/66 ; H01L23/64 ; G01R1/073 ; G01R31/28

Abstract:
The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such low impedance to a high frequency allows the die to operate at package-level speed, thus reducing yield loss at the packaging level. Each embodiment addresses a slightly different aspect of the overall wafer probe application. In each embodiment, however, the critical improvement of this disclosure is the location of the passive components used for supply filtering/decoupling relative to prior art. All three embodiments require a method to embed the passive components in close proximity to the pitch translation substrate or physically in the pitch translation substrate.
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