Invention Grant
- Patent Title: Fin field effect transistor device with reduced overlap capacitance and enhanced mechanical stability
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Application No.: US13906677Application Date: 2013-05-31
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Publication No.: US09793378B2Publication Date: 2017-10-17
- Inventor: Nicolas Loubet , Shom Ponoth , Prasanna Khare , Qing Liu , Balasubramanian Pranatharthiharan
- Applicant: STMicroelectronics, Inc. , International Business Machines Corporation
- Applicant Address: US TX Coppell US NY Armonk
- Assignee: STMicroelectronics, Inc.,International Business Machines Corporation
- Current Assignee: STMicroelectronics, Inc.,International Business Machines Corporation
- Current Assignee Address: US TX Coppell US NY Armonk
- Agency: Seed IP Law Group LLP
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/8234 ; H01L27/088 ; H01L29/78

Abstract:
Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.
Public/Granted literature
- US20140353753A1 FIN FIELD EFFECT TRANSISTOR DEVICE WITH REDUCED OVERLAP CAPACITANCE AND ENHANCED MECHANICAL STABILITY Public/Granted day:2014-12-04
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