Invention Grant
- Patent Title: Method and structure of making enhanced UTBB FDSOI devices
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Application No.: US15169495Application Date: 2016-05-31
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Publication No.: US09793396B2Publication Date: 2017-10-17
- Inventor: Qing Liu , Thomas Skotnicki
- Applicant: STMICROELECTRONICS, INC. , STMICROELECTRONICS (CROLLES 2) SAS
- Applicant Address: US TX Coppell FR Crolles
- Assignee: STMicroelectronics, Inc.,STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics, Inc.,STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: US TX Coppell FR Crolles
- Agency: Seed IP Law Group LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L29/10 ; H01L21/28 ; H01L29/08 ; H01L27/12 ; H01L29/423
Abstract:
An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.
Public/Granted literature
- US20160276480A1 METHOD AND STRUCTURE OF MAKING ENHANCED UTBB FDSOI DEVICES Public/Granted day:2016-09-22
Information query
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