Invention Grant
- Patent Title: Apparatus for monitoring operating conditions of a logic circuit to determine failure of one or more latches
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Application No.: US14631128Application Date: 2015-02-25
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Publication No.: US09798599B2Publication Date: 2017-10-24
- Inventor: Chittoor Parthasarathy , Abhishek Jain
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Amsterdam
- Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee Address: NL Amsterdam
- Agency: Gardere Wynne Sewell LLP
- Priority: IN3871/DEL/2011 20111228
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/14 ; G06F11/30 ; G06F11/07 ; H03K3/037 ; G06F11/16
Abstract:
An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.
Public/Granted literature
- US20150169394A1 APPARATUS FOR MONITORING OPERATING CONDITIONS OF A LOGIC CIRCUIT Public/Granted day:2015-06-18
Information query
