- 专利标题： Multi-mode set associative cache memory dynamically configurable to selectively select one or a plurality of its sets depending upon the mode
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申请号： US14891333申请日： 2014-12-14
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公开(公告)号： US09798668B2公开(公告)日： 2017-10-24
- 发明人: Douglas R. Reed
- 申请人： VIA Alliance Semiconductor Co., Ltd.
- 申请人地址： CN Shanghai
- 专利权人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- 当前专利权人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.
- 当前专利权人地址： CN Shanghai
- 代理商 E. Alan Davis; James W. Huffman
- 国际申请： PCT/IB2014/003231 WO 20141214
- 国际公布： WO2016/097810 WO 20160623
- 主分类号： G06F12/08
- IPC分类号： G06F12/08 ; G06F12/0864 ; G06F12/0846 ; G06F12/123 ; G06F12/128 ; G06F12/0804
摘要：
A cache memory stores 2^J-byte cache lines and includes an array of 2^N sets each holding tags each X bits, an input receives a Q-bit memory address, MA[(Q−1):0], having: a tag MA[(Q−1):(Q−X)] and an index MA[(Q−X−1):J]. Q is an integer at least (N+J+X−1). In a first mode: set selection logic selects one set using the index and LSB of the tag; comparison logic compares all but LSB of the tag with all but LSB of each tag in the selected set and indicates a hit if a match; otherwise allocation logic allocates into the selected set. In a second mode: the set selection logic selects two sets using the index; the comparison logic compares the tag with each tag in the selected two sets and indicates a hit if a match; and otherwise allocates into one set of the two selected sets.