- 专利标题: Bump structure design for stress reduction
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申请号: US15488972申请日: 2017-04-17
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公开(公告)号: US09799582B2公开(公告)日: 2017-10-24
- 发明人: Hsien-Wei Chen
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Haynes and Boone, LLP
- 主分类号: H01L23/31
- IPC分类号: H01L23/31 ; H01L23/29 ; H01L23/00
摘要:
Low stress bumps can be used to reduce stress and strain on bumps bonded to a substrate with different coefficients of thermal expansion (CTEs) from the die. The low stress bumps include multiple polymer layers. More than one type of bump is coupled to a die, with low stress bumps placed on areas subjected to high stress.
公开/授权文献
- US20170221789A1 BUMP STRUCTURE DESIGN FOR STRESS REDUCTION 公开/授权日:2017-08-03
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