A method for arranging an integrated circuit to correct a hold-time violation is provided. A first layout of the integrated circuit is prepared. The first layout includes a plurality of cells including a plurality of cell pins, wires connected between the cells, and one of the cell pins is located in a preservation area. The hold-time violation of the first layout is estimated to obtain an estimation result. A dummy wire structure is designed to be placed in the preservation area according to the estimation result to correct the hold-time violation. The dummy wire structure only contacts the cell pin in the preservation area. A second layout is generated according to the first layout and the designed dummy wire structure. The integrated circuit is arranged according to the second layout.