Invention Grant
- Patent Title: Planar fan-out wafer level packaging
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Application No.: US15072315Application Date: 2016-03-16
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Publication No.: US09806048B2Publication Date: 2017-10-31
- Inventor: Lizabeth Ann Keser , David Fraser Rae , Reynante Tamunan Alvarado
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Muncy, Geissler, Olds & Lowe
- Main IPC: H01L23/29
- IPC: H01L23/29 ; H01L23/00 ; H01L23/31 ; H01L21/56

Abstract:
A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and non-active sides of the die. The mold compound maybe above the top surface of the die in a fan-in area corresponding to a lateral width of the die and may also be in a fan-out area corresponding to an area that extends laterally away from a side surface of the die. The mold compound in the fan-in area need not be coplanar with the mold compound in at least a portion of the fan-out area. The device may also include a redistribution layer below the bottom surface of the die and below the mold compound, and may further include an interconnect below the redistribution layer and electrically coupled to the die through the redistribution layer. A portion of the redistribution layer may be in the fan-out area.
Public/Granted literature
- US20170271289A1 PLANAR FAN-OUT WAFER LEVEL PACKAGING Public/Granted day:2017-09-21
Information query
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