An integrated circuit device includes a clock gating circuit, which is configured to generate a first plurality of clocks in response to a first reference clock at a first frequency and a plurality of operation enable signals. A plurality of functional circuits are provided, which are responsive to respective ones of the first plurality of clocks. The plurality of functional circuits is configured to generate respective ones of the plurality of operation enable signals, with each of the plurality of operation enable signals having a first logic state that enables a respective clock within said clock gating circuit and a second logic state that disables the respective clock within said clock gating circuit.