A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=⅕ to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines. M array regions of the N array regions are configured to operate simultaneously. M is an integer. M/N=½ or 1.