发明授权
- 专利标题: Biased ESD circuit
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申请号: US14834554申请日: 2015-08-25
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公开(公告)号: US09812440B2公开(公告)日: 2017-11-07
- 发明人: Kenneth P. Snowdon , Taeghyun Kang , Yongliang Li
- 申请人: Fairchild Semiconductor Corporation
- 申请人地址: US CA San Jose
- 专利权人: Fairchild Semiconductor Corporation
- 当前专利权人: Fairchild Semiconductor Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Brake Hughes Bellermann LLP
- 主分类号: H02H9/04
- IPC分类号: H02H9/04 ; H01L27/02
摘要:
This document discusses, among other things, a biased electrostatic discharge (ESD) circuit and method configured to reduce capacitance of an ESD structure with little to no change in other ESD structure parameters. A bulk terminal of an ESD device can be negative biased to reduce a drain terminal to source terminal capacitance of the ESD device. A charge pump can be configured to provide a negative bias to the bulk terminal of the ESD device. In certain examples, the gate terminal of the ESD device can be coupled to the source terminal of the ESD device, such as through a resistor, and the source terminal can be coupled to ground.
公开/授权文献
- US20160064374A1 BIASED ESD CIRCUIT 公开/授权日:2016-03-03
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