Invention Grant
- Patent Title: Layout method, electronic device and connector
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Application No.: US14457469Application Date: 2014-08-12
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Publication No.: US09825388B2Publication Date: 2017-11-21
- Inventor: Chun-Yi Chou , Yu-Chang Pai , Teng-Yang Tan , Shih-Wei Tseng
- Applicant: NOVATEK MICROELECTRONICS CORP.
- Applicant Address: TW Hsinchu
- Assignee: NOVATEK MICROELECTRONICS CORP.
- Current Assignee: NOVATEK MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsinchu
- Agency: Rabin & Berdo, P.C.
- Priority: TW102134351A 20130924
- Main IPC: H05K1/11
- IPC: H05K1/11 ; H01R12/79 ; H01R13/6471 ; H05K1/18 ; H05K1/14 ; H05K3/30 ; H01R12/72 ; H01P5/12 ; H01B7/08 ; H05K1/02

Abstract:
A layout method applied to a connector is provided. The connector is electrically connected between a flexible printed circuit (FPC) and a printed circuit board (PCB). The FPC includes M pairs of differential lines and X shield lines. The PCB includes M pairs of differential lines and Z shield lines. The layout method includes following steps. Firstly, M pairs of conductive lines are disposed on the connector. The M conductive lines are correspondingly electrically connected to the M differential lines of the FPC and the M differential lines of the PCB. Then; Y conductive lines are disposed on the connector, wherein Y is smaller than X. Furthermore, at least one of the Y conductive lines is electrically connected to at least one of the X shield lines and at least one of the Z shield lines.
Public/Granted literature
- US20150085452A1 LAYOUT METHOD, ELECTRONIC DEVICE AND CONNECTOR Public/Granted day:2015-03-26
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