Invention Grant
- Patent Title: Nonvolatile RAM comprising a write circuit and a read circuit operating in parallel
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Application No.: US15266327Application Date: 2016-09-15
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Publication No.: US09858976B2Publication Date: 2018-01-02
- Inventor: Kazutaka Ikegami , Hiroki Noguchi
- Applicant: Kabushiki Kaisha Toshiba
- Applicant Address: JP Minato-ku
- Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee: KABUSHIKI KAISHA TOSHIBA
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neutsadt, L.L.P.
- Priority: JP2016-052297 20160316
- Main IPC: G11C7/00
- IPC: G11C7/00 ; G11C11/16 ; G11C15/02
Abstract:
According to one embodiment, a nonvolatile RAM includes a memory cell array, a first circuit being allowed to access the memory cell array in a write operation using a first pulse, and a second circuit being allowed to access the memory cell array in a read operation using a second pulse, the second circuit being allowed to operate in parallel with an operation of the first circuit. A width of the first pulse is longer than a width of the second pulse.
Public/Granted literature
- US20170270988A1 NONVOLATILE RAM Public/Granted day:2017-09-21
Information query
