Invention Grant
- Patent Title: Three-dimensional memory device with vertical semiconductor bit lines located in recesses and method of making thereof
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Application No.: US15207042Application Date: 2016-07-11
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Publication No.: US09859337B2Publication Date: 2018-01-02
- Inventor: Perumal Ratnam , Abhijit Bandyopadhyay , Christopher J. Petti
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Plano
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Plano
- Agency: The Marbury Law Group PLLC
- Main IPC: H01L27/24
- IPC: H01L27/24 ; H01L45/00 ; H01L23/528 ; H01L29/08 ; H01L29/10 ; H01L29/66 ; H01L21/225

Abstract:
A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate, semiconductor local bit lines extending perpendicular to the top surface of the substrate, and resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines. Each of the semiconductor local bit lines includes a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type, and a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.
Public/Granted literature
Information query
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