Invention Grant
- Patent Title: Stacked planar double-gate lamellar field-effect transistor
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Application No.: US15134155Application Date: 2016-04-20
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Publication No.: US09859375B2Publication Date: 2018-01-02
- Inventor: Josephine B. Chang , Michael A. Guillorn , Gen P. Lauer , Isaac Lauer , Jeffrey W. Sleight
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Nathan M. Rau
- Main IPC: H01L27/12
- IPC: H01L27/12 ; H01L29/10 ; H01L29/66 ; H01L29/78 ; H01L29/423 ; H01L29/06 ; H01L21/02 ; H01L21/321 ; H01L21/3213 ; H01L21/3065 ; H01L29/04 ; H01L29/40 ; H01L29/786 ; H01L21/306

Abstract:
A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.
Public/Granted literature
- US20160233304A1 STACKED PLANAR DOUBLE-GATE LAMELLAR FIELD-EFFECT TRANSISTOR Public/Granted day:2016-08-11
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