Invention Grant
- Patent Title: Semiconductor package having a source-down configured transistor die and a drain-down configured transistor die
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Application No.: US15089668Application Date: 2016-04-04
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Publication No.: US09881853B2Publication Date: 2018-01-30
- Inventor: Dirk Ahlers , Markus Dinkel
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/31 ; H01L21/48 ; H01L21/56 ; H02M7/00 ; H02M7/44

Abstract:
A semiconductor package includes a substrate, a first transistor die secured to the substrate and a second transistor die secured to the substrate. The first transistor die has a source terminal at a bottom side of the first transistor die which faces the substrate and a drain terminal and a gate terminal at a top side of the first transistor die which faces away from the substrate. The second transistor die has a drain terminal at a bottom side of the second transistor die which faces the substrate and a source terminal and a gate terminal at a top side of the second transistor die which faces away from the substrate. The package also includes a common electrical connection between the drain terminal of the first transistor die and the source terminal of the second transistor die.
Public/Granted literature
Information query
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