- Patent Title: Techniques for power supply topologies with capacitance management to reduce power loss associated with charging and discharging when cycling between power states
-
Application No.: US14496838Application Date: 2014-09-25
-
Publication No.: US09882472B2Publication Date: 2018-01-30
- Inventor: Nicholas P. Cowley , Ruchir Saraswat , Richard J. Goldman , David T. Bernard , Gordon J. Walsh , Michael Langan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Grossman, Tucker, Perreault & Pfleger, PLLC
- Main IPC: G05F1/56
- IPC: G05F1/56 ; H02M3/156 ; H02M1/36 ; H02M1/00
Abstract:
In at least one embodiment there is provided a method for managing bulk capacitance of a power supply system. The method includes precharging first and second bulk capacitors of the power supply system to approximately a first output voltage level and a second output voltage level, respectively; receiving a first command signal to generate, by the power supply, the first output voltage level; coupling the first bulk capacitance to load circuitry coupled to the power supply; receiving a second command signal to generate, by the power supply, the second output voltage level; and coupling the second bulk capacitance to the load circuitry coupled to the power supply.
Public/Granted literature
- US20160094121A1 POWER SUPPLY TOPOLOGIES WITH CAPACITANCE MANAGEMENT Public/Granted day:2016-03-31
Information query
IPC分类:
