Invention Grant
- Patent Title: High-speed receiver architecture
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Application No.: US15387246Application Date: 2016-12-21
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Publication No.: US09882648B2Publication Date: 2018-01-30
- Inventor: Oscar Ernesto Agazzi , Diego Ernesto Crivelli , Hugo Santiago Carrer , Mario Rafael Hueda , German Cesar Augusto Luna , Carl Grace
- Applicant: INPHI Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INPHI CORPORATION
- Current Assignee: INPHI CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Ogawa P.C.
- Agent Richard T. Ogawa
- Main IPC: H04B1/38
- IPC: H04B1/38 ; H04L5/16 ; H04B10/50 ; H04B10/69 ; H03M13/41 ; H04L25/02 ; H04B10/2507 ; H04B10/294 ; H04B3/23 ; H04B7/005 ; H04B1/04

Abstract:
A receiver (e.g., for a 10G fiber communications link) includes an interleaved ADC coupled to a multi-channel equalizer that can provide different equalization for different ADC channels within the interleaved ADC. That is, the multi-channel equalizer can compensate for channel-dependent impairments. In one approach, the multi-channel equalizer is a feedforward equalizer (FFE) coupled to a Viterbi decoder, for example a sliding block Viterbi decoder (SBVD); and the FFE and/or the channel estimator for the Viterbi decoder are adapted using the LMS algorithm.
Public/Granted literature
- US20170214468A1 HIGH-SPEED RECEIVER ARCHITECTURE Public/Granted day:2017-07-27
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