In order to perform processing corresponding to an instruction or a reaction at appropriate timing when a predetermined instruction is given or a reaction by a user is made while content is being outputted, a CPU detects instruction timing when a predetermined user instruction is given for data outputted while pieces of data constituting content are being sequentially outputted; stores the detected instruction timing in an instruction information memory; specifies predetermined timing that comes later than the instruction timing stored in the instruction information memory as timing for performing processing in accordance with the user's instruction; and performs the processing.