Invention Grant
- Patent Title: Gate signal line drive circuit
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Application No.: US15584074Application Date: 2017-05-02
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Publication No.: US09886928B2Publication Date: 2018-02-06
- Inventor: Takahiro Ochiai , Motoharu Miyamoto , Masahiro Hoshiba
- Applicant: Japan Display Inc.
- Applicant Address: JP Tokyo
- Assignee: Japan Display Inc.
- Current Assignee: Japan Display Inc.
- Current Assignee Address: JP Tokyo
- Agency: Typha IP LLC
- Priority: JP2013-202602 20130927
- Main IPC: G09G3/36
- IPC: G09G3/36

Abstract:
A gate signal line drive circuit whose power consumption is reduced, is provided. In the gate signal line drive circuit having plural basic circuits outputting respective gate signals, each basic circuit includes a high voltage application switching element to which a first basic clock signal having high voltage in a signal high period is input, a low voltage application switching element that turns on at timing starting a signal low period, and outputs a low voltage, and a first low voltage application on control element having an input terminal to which a second basic clock signal subsequent to the first basic clock signal is input, and which turns on according to the signal high period, and outputs the voltage of the second basic clock signal to the control terminal of the low voltage application switching element.
Public/Granted literature
- US20170236482A1 GATE SIGNAL LINE DRIVE CIRCUIT AND DISPLAY DEVICE Public/Granted day:2017-08-17
Information query
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