Invention Grant
- Patent Title: Reduced wake up delay for on-die routers
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Application No.: US15012181Application Date: 2016-02-01
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Publication No.: US09887849B2Publication Date: 2018-02-06
- Inventor: Dongkook Park , Akhilesh Kumar , Donglai Dai
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: H04L12/28
- IPC: H04L12/28 ; H04L12/12 ; G06F1/32 ; H03K19/00 ; H04J1/16

Abstract:
Techniques for power gating. A first on-die router has an output port to receive data from a switching fabric. The output port is placed in a power-gated state if there is no activity in the output port for a current cycle and no messages are to be received by the output port during a subsequent cycle. A second on-die router has an input port coupled with the output port of the first on-die router. The input port is placed in a power-gated state if an input port buffer is empty and the output port is not active. Power-gating of the input port and the output port are independent of each other.
Public/Granted literature
- US20160164689A1 REDUCED WAKE UP DELAY FOR ON-DIE ROUTERS Public/Granted day:2016-06-09
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