This technology relates to a semiconductor system. The semiconductor system may include a first semiconductor device capable of outputting a clock signal, a data strobe signal, and data; and a second semiconductor device capable of generating a division enable signal and a data input clock signal in response to the clock signal when performing a write operation, generating an internal strobe signal by dividing the data strobe signal in response to the division enable signal, and aligning the data in response to the internal strobe signal, wherein the first semiconductor device receives the division enable signal from the second semiconductor device and trains the data strobe signal so that the data strobe signal is output in a predetermined section.