Invention Grant
- Patent Title: Integration methods to fabricate internal spacers for nanowire devices
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Application No.: US15118838Application Date: 2014-03-24
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Publication No.: US09893167B2Publication Date: 2018-02-13
- Inventor: Seiyon Kim , Daniel A. Simon , Kelin J. Kuhn , Curtis W. Ward
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe Williamson & Wyatt P.C.
- International Application: PCT/US2014/031632 WO 20140324
- International Announcement: WO2015/147792 WO 20151001
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L29/423 ; H01L29/66 ; H01L21/764 ; H01L29/786

Abstract:
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing photo-definable spacer material in dimples etched adjacent to the channel region. Photo-definable material remains in the dimples by altering the etch characteristics of material outside of the dimples and selectively removing altered photo-definable material outside of the dimples.
Public/Granted literature
- US20170053998A1 INTEGRATION METHODS TO FABRICATE INTERNAL SPACERS FOR NANOWIRE DEVICES Public/Granted day:2017-02-23
Information query
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