发明授权
- 专利标题: Via blocking layer
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申请号: US15528427申请日: 2014-12-23
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公开(公告)号: US09899255B2公开(公告)日: 2018-02-20
- 发明人: Rami Hourani , Marie Krysak , Florian Gstrein , Ruth A. Brain , Mark T. Bohr
- 申请人: INTEL CORPORATION
- 申请人地址: US CA Santa Clara
- 专利权人: INTEL CORPORATION
- 当前专利权人: INTEL CORPORATION
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Finch & Maloney PLLC
- 国际申请: PCT/US2014/072252 WO 20141223
- 国际公布: WO2016/105402 WO 20160630
- 主分类号: H01L29/06
- IPC分类号: H01L29/06 ; H01L21/768 ; H01L23/528 ; H01L23/31
摘要:
Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.
公开/授权文献
- US20170330794A1 VIA BLOCKING LAYER 公开/授权日:2017-11-16
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