Invention Grant
- Patent Title: Via blocking layer
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Application No.: US15528427Application Date: 2014-12-23
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Publication No.: US09899255B2Publication Date: 2018-02-20
- Inventor: Rami Hourani , Marie Krysak , Florian Gstrein , Ruth A. Brain , Mark T. Bohr
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Finch & Maloney PLLC
- International Application: PCT/US2014/072252 WO 20141223
- International Announcement: WO2016/105402 WO 20160630
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/768 ; H01L23/528 ; H01L23/31

Abstract:
Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.
Public/Granted literature
- US20170330794A1 VIA BLOCKING LAYER Public/Granted day:2017-11-16
Information query
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