- 专利标题: Status register between test data I/O of scan port SUT
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申请号: US15435638申请日: 2017-02-17
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公开(公告)号: US09903912B2公开(公告)日: 2018-02-27
- 发明人: Gary L. Swoboda , Robert A. McGowan
- 申请人: TEXAS INSTRUMENTS INCORPORATED
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 Lawrence J. Bassuk; Charles A. Brill; Frank D. Cimino
- 主分类号: G01R31/317
- IPC分类号: G01R31/317 ; G01R31/3177 ; G01R31/3185 ; G06F11/22
摘要:
A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.
公开/授权文献
- US20170160344A1 STATUS REGISTER BETWEEN TEST DATA I/O OF SCAN PORT SUT 公开/授权日:2017-06-08