The present disclosure provides a gate driver circuit including at least one set of clock signal lines and multiple levels of shift registers arranged in a cascaded manner. Each set of the clock signal lines includes two clock signal lines. The multiple levels of shift registers is divided into at least one set, and each set of the clock signal lines corresponds to a set of the shift registers. One clock signal line in each set of the clock signal lines is connected to a resetting signal input end of a last-level shift register in the set of the shift registers corresponding to the set of the clock signal lines. The present disclosure further provides an array substrate, a display device and a method for driving the gate driver circuit.