Invention Grant
- Patent Title: Integrated circuit stress releasing structure
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Application No.: US14686783Application Date: 2015-04-15
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Publication No.: US09905515B2Publication Date: 2018-02-27
- Inventor: Chin-Chiang Chang , Tao Cheng
- Applicant: MEDIATEK INC.
- Applicant Address: TW Hsin-Chu
- Assignee: MediaTek Inc.
- Current Assignee: MediaTek Inc.
- Current Assignee Address: TW Hsin-Chu
- Agency: Wolf, Greenfield & Sacks, P.C.
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L23/31 ; H01L23/498

Abstract:
The present invention provides an integrated circuit (IC) package with stress releasing structure. The IC package comprises: a metal plane, a substrate, an IC chip, and an IC fill layer. The metal plane has at least one first etching line for separating the metal plane into a plurality of areas. The substrate is formed on metal layer. The IC chip is formed on the substrate, and the IC fill layer is formed around the IC chip. The at least one first etching line forms at least one half cut line in the metal plane and the substrate.
Public/Granted literature
- US20160043040A1 INTEGRATED CIRCUIT STRESS RELEASING STRUCTURE Public/Granted day:2016-02-11
Information query
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