Invention Grant
- Patent Title: Stress memorization and defect suppression techniques for NMOS transistor devices
-
Application No.: US15620082Application Date: 2017-06-12
-
Publication No.: US09905673B2Publication Date: 2018-02-27
- Inventor: Wen-Pin Peng , Min-hwa Chi
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Agent Nathan B. Davis
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/324 ; H01L21/225

Abstract:
Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.
Public/Granted literature
- US20170278949A1 STRESS MEMORIZATION AND DEFECT SUPPRESSION TECHNIQUES FOR NMOS TRANSISTOR DEVICES Public/Granted day:2017-09-28
Information query
IPC分类: