Invention Grant
- Patent Title: Trench liner passivation for dark current improvement
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Application No.: US13930189Application Date: 2013-06-28
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Publication No.: US09917003B2Publication Date: 2018-03-13
- Inventor: Cheng-Hsien Chou , Hung-Ling Shih , Tsun-Kai Tsao , Ming-Huei Shen , Kuo-Hwa Tzeng , Yeur-Luen Tu
- Applicant: Taiwan Semiconductor Manufacturing Co., LTD.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agent Maschoff Brennan
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/02

Abstract:
A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes a bottom portion and a top portion. The bottom portion has a lining oxide layer, a negatively-charged liner and a first silicon oxide. The lining oxide layer is peripherally enclosed by the semiconductor substrate, the negatively-charged liner is peripherally enclosed by the lining oxide layer, and the first silicon oxide is peripherally enclosed by the negatively-charged liner. The top portion adjoins the bottom portion, and has a second silicon oxide peripherally enclosed by and contacting the semiconductor substrate.
Public/Granted literature
- US20150001669A1 Trench Liner Passivation for Dark Current Improvement Public/Granted day:2015-01-01
Information query
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