Invention Grant
- Patent Title: Integrated circuits with a partially-depleted region formed over a bulk silicon substrate and methods for fabricating the same
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Application No.: US13961554Application Date: 2013-08-07
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Publication No.: US09917087B2Publication Date: 2018-03-13
- Inventor: Stefan Flachowksy , Juergen Faul , Jan Hoentschel
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Lorenz & Kopf, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L27/092

Abstract:
Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.
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