- 专利标题: Integrated circuit die having reduced defect group III-nitride layer and methods associated therewith
-
申请号: US15527287申请日: 2014-12-17
-
公开(公告)号: US09922826B2公开(公告)日: 2018-03-20
- 发明人: Sansaptak Dasgupta , Han Wui Then , Marko Radosavljevic , Robert S. Chau , Sanaz K. Gardner , Seung Hoon Sung
- 申请人: Intel Corporation
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 国际申请: PCT/US2014/070968 WO 20141217
- 国际公布: WO2016/099494 WO 20160623
- 主分类号: H01L21/02
- IPC分类号: H01L21/02 ; H01L29/20 ; H01L29/225 ; H01L29/205 ; H01L29/32 ; H01L29/08 ; H01L29/06 ; H01L21/027 ; H01L29/66 ; H01L21/8258 ; H01L27/06 ; H01L29/778 ; H01L29/22 ; H01L23/00 ; H01L27/092
摘要:
Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.
公开/授权文献
信息查询
IPC分类: